The present technique relates to the field of integrated circuits, and in particular to techniques for generating the layout of a circuit block for such an integrated circuit. The circuit block may represent the entire integrated circuit or a component within the integrated circuit.
In the design of semiconductor integrated circuits, it is known to provide automated tools which use a functional design of a planned circuit block identifying the logical operation that that circuit block is to perform (for example in the form of a gate level netlist or a Register Transfer Level representation of the design) and a cell library providing a set of cells (the cells defining circuit elements, and being “building blocks” for putting together the layout of the circuit block according to the functional design) in order to generate the layout of the circuit block.
In particular, the automated tool may take the form of a place and route tool which places the required cells within a floorplan and then performs a routing operation to determine routing paths to be provided within a number of metal layers in order to interconnect the various cells, so that collectively the cells will perform the required logical operation of the circuit block.
As the complexity of the required circuit blocks increases, it is becoming more and more difficult to accommodate all of the required routing paths within the available metal layers, and it is sometimes the case that the area required for the circuit block may be larger than it would otherwise need to be, so as to provide sufficient space for all of the various routing paths to be provided.
Accordingly, it would be desirable to provide improved techniques for accommodating the required routing paths within the layout of a circuit block.